In general, a semiconductor memory device enables peripheral circuits to store data or externally output the stored data in an active state, and disables unnecessary peripheral circuits in a standby state to minimize power consumption. When the semiconductor memory device is maintained in the standby state for a long time, it enters into a deep power down mode to stop the operation of the peripheral circuits to reduce power consumption.
The deep power down mode is controlled according to an external command in the semiconductor memory device. That is, the semiconductor memory device enters into or ends the deep power down mode according to a state of signals CS, RAS, CAS, WE and CKE input through the memory device's external signal pin after a precharge time tRP from a precharge command. This operation is synchronized with a clock signal.
For example, when the chip select signal CS has a low level, the row address strobe signal RAS has a high level, the column address strobe signal CAS has a high level, the write enable signal WE has a low level and the clock enable signal CKE has a low level, the semiconductor memory device is synchronized by the clock signal CLK to enter into the deep power down mode. And when the clock enable signal CLK is transited to a high level, the semiconductor memory device ends the deep power down mode. When the semiconductor memory device enters into the deep power down mode, it intercepts power of some power circuits to reduce power consumption.
However, the aforementioned method restrictively reduces power consumption, and thus cannot control a specific power circuit which may generate mis-operation. For example, a reference voltage generator or power up circuit is difficult to control. Accordingly, the semiconductor memory device fails to stop the operation of such circuits, but intercepts power of some controllable circuits. As a result, it is difficult to reduce unnecessary power consumption sufficiently. In particular, conventional semiconductor memory devices cannot effectively control a micro bridge generated between internal circuits or between wires.